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Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK950
FEATURES
2 selectable differential inputs 4.8 GHz operating frequency 75 fs rms broadband random jitter On-chip input terminations 3.3 V power supply
FUNCTIONAL BLOCK DIAGRAM
LVPECL
ADCLK950
Q0 Q0 Q1 Q1 Q2 Q2 Q3
APPLICATIONS
Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation
VREF 0
REFERENCE Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7
VT0 CLK0
GENERAL DESCRIPTION
The ADCLK950 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter. The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx VREFx pin is available for biasing ac-coupled inputs. The ADCLK950 features 10 full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The output stages are designed to directly drive 800 mV each side into 50 terminated to VCC - 2 V for a total differential output swing of 1.6 V. The ADCLK950 is available in a 40-lead LFCSP and specified for operation over the standard industrial temperature range of -40C to +85C.
CLK0 VT1 CLK1 CLK1
IN_SEL
Q7 REFERENCE Q8 Q8 Q9
08279-001
VREF 1
Q9
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
ADCLK950 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics ............................................................. 3 Absolute Maximum Ratings............................................................ 5 Determining Junction Temperature .......................................... 5 ESD Caution .................................................................................. 5 Thermal Performance .................................................................. 5 Pin Configuration and Function Descriptions..............................6 Typical Performance Characteristics ..............................................7 Functional Description .....................................................................9 Clock Inputs ...................................................................................9 Clock Outputs ................................................................................9 Clock Input Select (IN_SEL) Settings...................................... 10 PCB Layout Considerations ...................................................... 10 Input Termination Options ....................................................... 11 Outline Dimensions ....................................................................... 12 Ordering Guide .......................................................................... 12
REVISION HISTORY
7/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADCLK950 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ column) values are given for VCC - VEE = 3.3 V and TA = 25C, unless otherwise noted. Minimum (Min column) and maximum (Max column) values are given over the full VCC - VEE = 3.3 V 10% and TA = -40C to +85C variation, unless otherwise noted. Table 1. Clock Inputs and Outputs
Parameter DC INPUT CHARACTERISTICS Input Common Mode Voltage Input Differential Range Input Capacitance Input Resistance Single-Ended Mode Differential Mode Common Mode Input Bias Current Hysteresis DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Output Voltage Differential Reference Voltage Output Voltage Output Resistance Symbol VICM VID CIN Min VEE + 1.5 0.4 0.4 50 100 50 20 10 VOH VOL VOD VREF VCC - 1.26 VCC - 1.99 610 (VCC + 1)/2 235 VCC - 0.76 VCC - 1.54 960 Typ Max VCC - 0.1 3.4 Unit V V p-p pF k A mV V V mV V Test Conditions/Comments
1.7 V between input pins
Open VTx
50 to (VCC - 2.0 V) 50 to (VCC - 2.0 V) 50 to (VCC - 2.0 V) -500 A to +500 A
Table 2. Timing Characteristics
Parameter AC PERFORMANCE Maximum Output Frequency Symbol Min 4.5 Typ 4.8 Max Unit GHz Test Conditions/Comments See Figure 4 for differential output voltage vs. frequency, >0.8 V differential output swing 20% to 80% measured differentially VICM = 2 V, VID = 1.6 V p-p
Output Rise Time Output Fall Time Propagation Delay Temperature Coefficient Output-to-Output Skew 1 Part-to-Part Skew Additive Time Jitter Integrated Random Jitter Broadband Random Jitter 2 Crosstalk-Induced Jitter 3 CLOCK OUTPUT PHASE NOISE Absolute Phase Noise fIN = 1 GHz
tR tF tPD
40 40 175
75 75 210 50 9
90 90 245 28 45
ps ps ps fs/C ps ps fs rms fs rms fs rms
VID = 1.6 V p-p BW = 12 kHz - 20 MHz, CLK = 1 GHz VID = 1.6 V p-p, 8 V/ns, VICM = 2 V
28 75 90
-119 -134 -145 -150 -150
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Input slew rate > 1 V/ns (see Figure 11, the phase noise plot, for more details) @100 Hz offset @1 kHz offset @10 kHz offset @100 kHz offset >1 MHz offset
1 2
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method. 3 This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.
Rev. 0 | Page 3 of 12
ADCLK950
Table 3. Input Select Control Pin
Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance Symbol VIH VIL IIH IIL Min VCC - 0.4 VEE Typ Max VCC 1 100 0.6 Unit V V A mA pF
2
Table 4. Power
Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2
1 2
Symbol VCC - VEE IVEE IVCC PSRVCC PSRVCC
Min 2.97
Typ
Max 3.63
Unit V mA mA ps/V dB
Test Conditions/Comments 3.3 V + 10% Static VCC - VEE = 3.3 V 10% VCC - VEE = 3.3 V 10% VCC - VEE = 3.3 V 10% VCC - VEE = 3.3 V 10%
106 346 <3 28
130 390
Change in tPD per change in VCC. Change in output swing per change in VCC.
Rev. 0 | Page 4 of 12
ADCLK950 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Supply Voltage VCC - VEE Input Voltage CLK0, CLK1, CLK0, CLK1, IN_SEL CLK0, CLK1, CLK0, CLK1 to VTx Pin (CML, LVPECL Termination) CLK0, CLK1 to CLK0, CLK1 Input Termination, VTx to CLK0, CLK1, CLK0, and CLK1 Maximum Voltage on Output Pins Maximum Output Current Voltage Reference (VREFx) Operating Temperature Range Ambient Junction Storage Temperature Range Rating 6V VEE - 0.5 V to VCC + 0.5 V 40 mA 1.8 V 2 V VCC + 0.5 V 35 mA VCC to VEE -40C to +85C 150C -65C to +150C
DETERMINING JUNCTION TEMPERATURE
To determine the junction temperature on the application printed circuit board (PCB), use the following equation: TJ = TCASE + (JT x PD) where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the customer at the top center of the package. JT is from Table 6. PD is the power dissipation. Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approximation of TJ by the equation TJ = TA + (JA x PD) where TA is the ambient temperature (C). Values of JB are provided in Table 6 for package comparison and PCB design considerations.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
THERMAL PERFORMANCE
Table 6.
Parameter Junction-to-Ambient Thermal Resistance Still Air 0 m/sec Air Flow Moving Air 1 m/sec Air Flow 2.5 m/sec Air Flow Junction-to-Board Thermal Resistance Moving Air 1 m/sec Air Flow Junction-to-Case Thermal Resistance Moving Air Die-to-Heatsink Junction-to-Top-of-Package Characterization Parameter Still Air 0 m/sec Air Flow
1
Symbol JA
Description Per JEDEC JESD51-2
Value 1
Unit
46.1 JMA Per JEDEC JESD51-6 40.3 36.2 JB Per JEDEC JESD51-8 28.7 JC Per MIL-STD 883, Method 1012.1 8.3 JT Per JEDEC JESD51-2 0.6
C/W C/W C/W
C/W
C/W
C/W
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations.
Rev. 0 | Page 5 of 12
ADCLK950 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
40 39 38 37 36 35 34 33 32 31 VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VCC
IN_SEL 1 CLK0 2 CLK0 3 VREF 0 4 VT0 5 CLK1 6 CLK1 7 VT1 8 VREF 1 9 VEE 10
PIN 1 INDICATOR
ADCLK950
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
VCC NC NC Q4 Q4 Q5 Q5 NC NC VCC
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11, 20, 21, 30, 31, 40 12, 13 14, 15 16, 17 18, 19 22, 23, 28, 29 24, 25 26, 27 32, 33 34, 35 36, 37 38, 39 (41) Mnemonic IN_SEL CLK0 CLK0 VREF0 VT0 CLK1 CLK1 VT1 VREF1 VEE VCC Q9, Q9 Q8, Q8 Q7, Q7 Q6, Q6 NC Q5, Q5 Q4, Q4 Q3, Q3 Q2, Q2 Q1, Q1 Q0, Q0 EPAD Description Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs. Differential Input (Positive) 0. Differential Input (Negative) 0. Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs. Center Tap. Center tap of a 100 input resistor for CLK0 and CLK0 inputs. Differential Input (Positive) 1. Differential Input (Negative) 1. Center Tap. Center tap of a 100 input resistor for CLK1 and CLK1 inputs. Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs. Negative Supply Pin. Positive Supply Pin. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. No Connection Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. EPAD must be connected to VEE.
Rev. 0 | Page 6 of 12
08279-002
NOTES 1. NC = NO CONNECT. 2. EPAD MUST BE SOLDERED TO VEE POWER PLANE.
VCC Q9 Q9 Q8 Q8 Q7 Q7 Q6 Q6 VCC
11 12 13 14 15 16 17 18 19 20
ADCLK950 TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0 V, VICM = VREFx, TA = 25C, clock outputs terminated at 50 to VCC - 2 V, unless otherwise noted.
C3
C4
C3
C4
C4 100mV/DIV 500ps/DIV
08279-003
100mV/DIV
100ps/DIV
Figure 3. LVPECL Output Waveform @ 200 MHz
1.8 1.7
DIFFERENTIAL OUTPUT VOLTAGE (V)
Figure 6. LVPECL Output Waveform @ 1000 MHz
214 213
PROPAGATION DELAY (ps)
1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5
08279-004
212 211 210 209 208 207 -40
0
1000
2000
3000
4000
5000
-20
0
20
40
60
80
FREQUENCY (MHz)
TEMPERATURE (C)
Figure 4. Differential Output Voltage vs. Frequency, VID > 1.1 V p-p
225 220
PROPAGATION DELAY (ps)
Figure 7. Propagation Delay vs. Temperature, VID = 1.6 V p-p
230
PROPAGATION DELAY (ps)
215 210 205 200 195 190 185
08279-005
220
+85C 210 +25C 200
-40C
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
DIFFERENTIAL INPUT VOLTAGE SWING (V)
DC COMMON-MODE VOLTAGE (V)
Figure 5. Propagation Delay vs. Differential Input Voltage
Figure 8. Propagation Delay vs. DC Common-Mode Voltage vs. Temperature, Input Slew Rate > 25 V/ns
Rev. 0 | Page 7 of 12
08279-008
180
190 0.9
08279-007
0.4
08279-006
C3
ADCLK950
1.56
DIFFERENTIAL OUTPUT VOLTAGE SWING (V)
-90 -100 -40C
PHASE NOISE (dBc/Hz)
1.54 1.52 1.50 1.48 1.46 1.44 1.42 2.75
ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672), WENZEL 5x MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A WENZEL 2x MULTIPLIER (P/N LNDD-500-14-14-1-D).
-110 -120 -130 -140 -150 -160 -170 10 ADCLK950
+25C
+85C
CLOCK SOURCE 100 1k 10k 100k 1M 10M 100M
08279-011 08279-012
2.85
2.95
3.05
3.15
3.25
3.35
3.45
3.55
3.65
3.75
POWER SUPPLY (V)
08279-009
FREQUENCY OFFSET (Hz)
Figure 9. Differential Output Voltage Swing vs. Power Supply Voltage vs. Temperature, VID = 1.6 V p-p
400 ICC 350 300 250 200 150 IEE 100 50 2.75
RANDOM JITTER (fS rms) SUPPLY CURRENT (mA)
Figure 11. Absolute Phase Noise Measured @1 GHz
300
250
200
+85C +25C -40C
150
100
50
08279-010
0 0 5 10 15 20 25 INPUT SLEW RATE (V/ns)
3.00
3.25 SUPPLY VOLTAGE (V)
3.50
3.75
Figure 10. Power Supply Current vs. Power Supply Voltage vs. Temperature, All Outputs Loaded (50 to VCC - 2 V)
Figure 12. RMS Random Jitter vs. Input Slew Rate, VID Method
Rev. 0 | Page 8 of 12
ADCLK950 FUNCTIONAL DESCRIPTION
CLOCK INPUTS
The ADCLK950 accepts a differential clock input from one of two inputs and distributes the selected clock to all 10 LVPECL outputs. The maximum specified frequency is the point at which the output voltage swing is 50% of the standard LVPECL swing (see Figure 4). See the functional block diagram (Figure 1) and the General Description section for more clock input details. See Figure 19 through Figure 23 for various clock input termination schemes. Output jitter performance is degraded by an input slew rate below 4 V/ns, as shown in Figure 12. The ADCLK950 is specifically designed to minimize added random jitter over a wide input slew rate range. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate. Input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics. Thevenin-equivalent termination uses a resistor network to provide 50 termination to a dc voltage that is below VOL of the LVPECL driver. In this case, VS_DRV on the ADCLK950 should equal VS of the receiving buffer. Although the resistor combination shown (in Figure 15) results in a dc bias point of VS_DRV - 2 V, the actual common-mode voltage is VS_DRV - 1.3 V because there is additional current flowing from the ADCLK950 LVPECL driver through the pull-down resistor. LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter follower LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue.
VS_DRV
ADCLK950
Z0 = 50 VCC - 2V Z0 = 50
VS = VS_DRV
CLOCK OUTPUTS
The specified performance necessitates using proper transmission line terminations. The LVPECL outputs of the ADCLK950 are designed to directly drive 800 mV into a 50 cable or into microstrip/stripline transmission lines terminated with 50 referenced to VCC - 2 V, as shown in Figure 14. The LVPECL output stage is shown in Figure 13. The outputs are designed for best transmission line matching. If high speed signals must be routed more than a centimeter, either the microstrip or the stripline technique is required to ensure proper transition times and to prevent excessive output ringing and pulse width dependent propagation delay dispersion.
VCC
50
08279-014
50
LVPECL
Figure 14. DC-Coupled, 3.3 V LVPECL
VS_DRV VS_DRV
ADCLK950
50 SINGLE-ENDED (NOT COUPLED) 50 127 127
VS
LVPECL
Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination
VS_DRV
ADCLK950
Z0 = 50 50 Z0 = 50
VS = VS_DRV
50
08279-016
Qx Qx
50
LVPECL
Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination
08279-013
VEE
VS_DRV
ADCLK950
0.1nF 100 DIFFERENTIAL 100 (COUPLED) 0.1nF TRANSMISSION LINE
VS
Figure 13. Simplified Schematic Diagram of the LVPECL Output Stage
Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line
Rev. 0 | Page 9 of 12
08279-017
Figure 14 through Figure 17 depict various LVPECL output termination schemes. When dc-coupled, VS of the receiving buffer should match VS_DRV.
LVPECL
200
200
08279-015
83
83
ADCLK950
CLOCK INPUT SELECT (IN_SEL) SETTINGS
A Logic 0 on the IN_SEL pin selects the Input CLK0 and Input CLK0. A Logic 1 on the IN_SEL pin selects Input CLK1 and Input CLK1. return path. If the inputs are dc-coupled to a source, take care to ensure that the pins are within the rated input differential and common-mode ranges. If the return is floated, the device exhibits a 100 cross termination, but the source must then control the common-mode voltage and supply the input bias currents. There are ESD/clamp diodes between the input pins to prevent the application from developing excessive offsets to the input transistors. ESD diodes are not optimized for best ac performance. When a clamp is required, it is recommended that appropriate external diodes be used.
PCB LAYOUT CONSIDERATIONS
The ADCLK950 buffer is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes for both the negative supply (VEE) and the positive supply (VCC) planes as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. The following references to the GND plane assume that the VEE power plane is grounded for LVPECL operation. Note that for ECL operation, the VCC power plane becomes the ground plane. It is also important to adequately bypass the input and output supplies. Place a 1 F electrolytic bypass capacitor within several inches of each VCC power supply pin to the GND plane. In addition, place multiple high quality 0.001 F bypass capacitors as close as possible to each of the VCC supply pins, and connect the capacitors to the GND plane with redundant vias. Carefully select high frequency bypass capacitors for minimum inductance and ESR. To improve the effectiveness of the bypass at high frequencies, minimize parasitic layout inductance. Also, avoid discontinuities along input and output transmission lines that can affect jitter performance. In a 50 environment, input and output matching have a significant impact on performance. The buffer provides internal 50 termination resistors for both CLKx and CLKx inputs. Normally, the return side is connected to the reference pin that is provided. Carefully bypass the termination potential using ceramic capacitors to prevent undesired aberrations on the input signal due to parasitic inductance in the termination
Exposed Metal Paddle
The exposed metal paddle on the ADCLK950 package is both an electrical connection and a thermal enhancement. For the device to function properly, the paddle must be properly attached to the VEE power plane. When properly mounted, the ADCLK950 also dissipates heat through its exposed paddle. The PCB acts as a heat sink for the ADCLK950. The PCB attachment must provide a good thermal path to a larger heat dissipation area. This requires a grid of vias from the top layer down to the VEE power plane (see Figure 18). The ADCLK950 evaluation board (ADCLK950/PCBZ) provides an example of how to attach the part to the PCB.
VIAS TO VEE POWER PLANE
Figure 18. PCB Land for Attaching Exposed Paddle
Rev. 0 | Page 10 of 12
08279-018
ADCLK950
INPUT TERMINATION OPTIONS
VCC V Tx 50 CLKx CLKx
VREF x
VREF x VTx
50
50 CLKx CLKx
50
08279-019
CONNECT VTx TO VCC.
CONNECT VTx TO VREF x.
Figure 19. DC-Coupled CML Input Termination
Figure 21. AC-Coupled Input Termination, Such as LVDS and LVPECL
VREF x
VCC
V Tx 50 CLKx CLKx
50
50
0.01F (OPTIONAL)
VREF x V Tx 50 CLKx CLKx
08279-020
50
ADCLK950
CONNECT VTx, VREF x, AND CLKx. PLACE A BYPASS CAPACITOR FROM VTx TO GROUND. ALTERNATIVELY, VTx, VREF x, AND CLKx CAN BE CONNECTED, GIVING A CLEANER LAYOUT AND A 180 PHASE SHIFT.
08279-021
ADCLK950
ADCLK950
ADCLK950
Figure 20. DC-Coupled LVPECL Input Termination
Figure 22. AC-Coupled Single-Ended Input Termination
VREF x V Tx 50 CLKx CLKx 50
ADCLK950
Figure 23. DC-Coupled 3.3 V CMOS Input Termination
Rev. 0 | Page 11 of 12
08279-023
08279-022
ADCLK950 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX 0.60 MAX
29 28 40 1
PIN 1 INDICATOR 3.05 2.90 SQ 2.75
PIN 1 INDICATOR
5.75 BSC SQ
0.50 BSC
EXPOSED PAD
0.50 0.40 0.30
TOP VIEW
20 19
11
10
0.25 MIN
BOTTOM VIEW
1.00 0.85 0.80 SEATING PLANE
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
4.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
082708-A
0.30 0.23 0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 24. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-40-8) Dimensions shown in millimeters
ORDERING GUIDE
Model ADCLK950BCPZ 1 ADCLK950BCPZ-REEL71 ADCLK950/PCBZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ Evaluation Board
Package Option CP-40-8 CP-40-8
Z = RoHS Compliant Part.
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08279-0-7/09(0)
Rev. 0 | Page 12 of 12

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